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29 "Other" IP

1
UHS2 Device Phy
This UHS2PHY IP solution for UHS-II interface that SD Association is working on the standardization as the new ultra high speed interface for both SDHC and SDXC. By using this unique SerDes technolog...

2
UHS2 Host Phy
This UHS2PHY IP solution for UHS-II interface that SD Association is working on the standardization as the new ultra high speed interface for both SDHC and SDXC. By using this unique SerDes technolog...

3
ADC controller for Faraday internal use.
ADC controller for Faraday internal use.

4
AHB-Lite Slave wrapper, it is a protocol converter from AHB to AHB lite.
AHB-Lite Slave wrapper, it is a protocol converter from AHB to AHB lite.

5
AHB-to-APB simple bridge.
AHB-to-APB simple bridge.

6
Cipher coprocess for encryption/decryption of DES/Triple-DES/AES algorithm.
Cipher coprocess for encryption/decryption of DES/Triple-DES/AES algorithm.

7
Intelligent Energy Controller for voltage and frequency scaling.
Intelligent Energy Controller for voltage and frequency scaling.

8
SD host controller wih ahb interface, compliant with the SD Host Controller Standard Specification Version 2.00
SD host controller wih ahb interface, compliant with the SD Host Controller Standard Specification Version 2.00

9
The FTWDT011 is an independent watchdog peripheral which offers a clocked by a dedicated clock through the external port and thus stays active event if the main clock fails. It can serve to detect and resolve malfunctions due to software failure, and to t
The FTWDT011 is an independent watchdog peripheral which offers a clocked by a dedicated clock through the external port and thus stays active event if the main clock fails. It can serve to detect and...

10
Timer with APB interface and PWM output function
Timer with APB interface and PWM output function

11
0.035... 100 MHz intermediate-frequency amplifier
IFA consists of 6-stage amplifier with tunable gain, AGC system, linear output buffer for differential analog output. Gain is sequentially reduced from the last stage to the first stage. This method a...

12
0.8 to 25 MHz Intermediate-frequency amplifier
IFA consists of 4-stage amplifier with tunable gain, AGC system, linear output buffer for differential analog output, analog-digital converter for digital output and a detector of output level. The am...

13
15 to 2780 kHz amplifier with band-pass filter
Band-pass filter (BPF) includes LPF and two stages amplifier. All stages input DC are decoupled and compensated. LPF is based on Chebyshev 4th stage filter. BPF has constant gain 20 dB. Two stage ampl...

14
9-bit programmable ECL HF divider
The 9-bit programmable ECL high-frequency divider is a set of serially connected dividers with the varied dividing ratio 2/3 which is able to scale the structure either into minimum dividing ratio dec...

15
AXI Fabric Package for Scalable SoC Applications
AndeShape AE300 package in this document refers to two licensable Andes platform products, the AE300FB AXI fabric and the AE300EP example platform. The AE300FB AXI fabric package includes AXI intercon...

16
Reed Solomon Forward Error Correction Encoder Decoder
Comcores RS FEC IP Core is a versatile solution for robust error correction in a wide range of applications, such as wireless communication, data storage, digital broadcasting, and beyond. Comcores RS...

17
Slave HSSL Controller
The logiHSSL IP core enables high-speed communication between microcontrollers of Infineon's AURIX family (TC2xx and TC3xx) and Xilinx SoC (System-on-Chip), MPSoC (MultiProcessor SoC) and FPGA (Field ...

18
Supporting ONFI 4.2, 4.1, 4.0 and ONFI 3
Dolphin Technology provides a complete NAND FLASH I/O library package. The package includes configurable IO's, power cells, fillers, spacers and analog cells. ESD and latch-up prevention structures ar...

19
Supporting ONFI 5.0, 4.2, 4.1, 4.0 and ONFI 3
Dolphin Technology provides a complete NAND FLASH I/O library package. The package includes configurable IO's, power cells, fillers, spacers and analog cells. ESD and latch-up prevention structures ar...

20
Supporting ONFI 5.0, 4.2, 4.1, 4.0 and ONFI 3 - TSMC 40nm 40G,LP,LP_eF,ULP,ULP_eF
Dolphin Technology provides a complete NAND FLASH I/O library package. The package includes configurable IO's, power cells, fillers, spacers and analog cells. ESD and latch-up prevention structures ar...

21
Supporting ONFI 6.0, 5.0, 4.2, 4.1, 4.0 and ONFI 3
Dolphin Technology provides a complete NAND FLASH I/O library package. The package includes configurable IO's, power cells, fillers, spacers and analog cells. ESD and latch-up prevention structures ar...

22
Supporting ONFI 6.0, 5.0, 4.2, 4.1, 4.0 and ONFI 3
Dolphin Technology provides a complete NAND FLASH I/O library package. The package includes configurable IO's, power cells, fillers, spacers and analog cells. ESD and latch-up prevention structures ar...

23
Broadcast quality video encoder for all NTSC and PAL video standards
PT8 is a broadcast quality video encoder IP Core supporting all NTSC and PAL standards.

24
Hardware NLM (Non-Local-Mean) Video Noise Reduction IP core
NLM (Non Local Mean) is a noise reduction algorithm wherein the value of each pixel is determined a rectangle of pixels around that pixel (a “center patch”) with all identically-sized rectangles of pi...

25
Path tracing/Ray tracing accelerator
RayCore Lite IP is designed based on MIMD architecture. This approach enables more efficient execution of independent parallel tasks – each ray is regarded as an independent instruction. Due to this a...

26
Post Quantum Secure Boot
The TESIC-310 IP is a turnkey solution to provide a secure boot facility to an SoC. It implements the Post Quantum secure Leighton-Micali Signature (LMS) as specified in NIST SP800-208. The TESIC-310 ...

27
MPEG Transport Stream Multiplexing & Encapsulation Engine
The MTS-E core multiplexes and encapsulates audio, video and metadata streams in a single MPEG Transport Stream (TS), and optionally encapsulates the TS packets in Real-Time Transport Protocol (RTP) p...

28
GPU, 2D Composition engine for Android
The DMP ant100 is ultra tiny 2D composition engine which is the fastest 2D and pixel processing pipeline up to 8K x 8K resolution. The DMP ant100 can blend, scale, animate, layer , filter, process, an...

29
Vector Graphics IP core supporting OpenVG1.1 subset
The ant200 is the world’s smallest Vector Graphics IP core supporting OpenVG1.1 subset.

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